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dg528/529 vishay siliconix document number: 70068 p-32167?rev. c, 15-nov-93 www.vishay.com 1 latchable single 8-ch/differential 4-ch analog multiplexers

low r ds(on) : 270 44-v power supply rating on-board address latches break-before-make low leakage?i d(on) : 30 pa improved system accuracy microporcessor bus compatible easily interfaced reduced crosstalk data acquisition systems automatic test equipment avionics and military systems medical instrumentation

the dg528 is an 8-channel single-ended analog multiplexer designed to connect one of eight inputs to a common output as determined by a 3-bit binary address (a 0 , a 1 , a 2 ). DG529, a 4-channel dual analog multiplexer, is designed to connect one of four differential inputs to a common differential output as determined by its 2-bit binary address (a 0 , a 1 ) logic. these analog multiplexers have on-chip address and control latches to simplify design in microprocessor based applications. break-before-make switching action protects against momentary shorting of the input signals. the dg528/529 are built on the improved plus-40 cmos process. a buried layer prevents latchup. the on chip ttl-compatible address latches simplify digital interface design and reduce board space in data acquisition systems, process controls, avionics, and ate.

wr d rs s 8 a 0 a 1 en a 2 v? gnd s 1 v+ s 2 s 5 s 3 s 6 s 4 s 7 dual-in-line decoders/drivers 1 2 3 4 5 6 7 8 18 17 16 15 14 13 12 11 top view 910 latches en a 2 v? gnd s 1 v+ s 2 s 5 s 3 s 6 plcc 14 15 16 17 18 8 7 6 5 4 1 2 319 20 11 10 913 12 top view 4 d nc 8 7 a wr nc rs a latches decoders/drivers 0 1 s s s wr d a rs d b a 0 a 1 en gnd v? v+ s 1a s 1b s 2a s 2b s 3a s 3b s 4a s 4b dual-in-line decoders/drivers 1 2 3 4 5 6 7 8 18 17 16 15 14 13 12 11 top view 910 latches dg528 dg528 DG529
dg528/529 vishay siliconix www.vishay.com 2 document number: 70068 p-32167 ? rev. c, 15-nov-93

8-channel single-ended multiplexer a 2 a 1 a 0 en wr rs on switch latching x x x x 1 maintains previous switch condition reset x x x x x 0 none (latches cleared) transparent operation x x x 0 0 1 none 0 0 0 1 0 1 1 0 0 1 1 0 1 2 0 1 0 1 0 1 3 0 1 1 1 0 1 4 1 0 0 1 0 1 5 1 0 1 1 0 1 6 1 1 0 1 0 1 7 1 1 1 1 0 1 8 differential 4-channel multiplexer a 0 en wr rs on switch latching x x 1 maintains previous switch condition reset x x x 0 none (latches cleared) transparent operation x 0 0 1 none 0 1 0 1 1 1 1 0 1 2 0 1 0 1 3 1 1 0 1 4 logic ? 0 ? = v al 0.8 v logic ? 1 ? = v ah 2.4 v x = don ? t care

temp range package part number 18-pin plastic dip dg528cj 0 to 70 c 20-pin plcc dg528dn ? 25 to 85 c dg528bk dg528ak ? 55 to 125 c 18-pin cerdip dg528ak/883 5962-8768901va

temp range package part number 0 to 70 c 18-pin plastic dip DG529cj ? 25 to 85 c DG529bk ? 55 to 125 c 18-pin cerdip DG529ak/883

voltage referenced to v ? v+ 44 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs a , v s , v d (v ? ) ? 2 v to (v+) +2 v or . . . . . . . . . . . . . . . . . . . . . . . . 30 ma, whichever occurs first current (any terminal except s or d) 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current, s or d 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peak current, s or d (pulsed at 1 ms, 10% duty cycle max) 40 ma . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature (ak, bk suffix) ? 65 to 150 c . . . . . . . . . . . . . . (cj, dn suffix) ? 65 to 125 c . . . . . . . . . . . . . . power dissipation (package) b 18-pin plastic dip c 470 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-pin cerdip d 900 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-pin plcc e 800 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on s x , d x or in x exceeding v+ or v ? will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads soldered or welded to pc board. c. derate 6.3 mw/ c above 75 c. d. derate 1.2 mw/ c above 75 c. e. derate 10 mw/ c above 75 c.
dg528/529 vishay siliconix document number: 70068 p-32167 ? rev. c, 15-nov-93 www.vishay.com 3

test conditions unless otherwise specified a suffix ? 55 to 125 c b, c, d suffix ? 40 to 85 c parameter symbol v+ = 15 v, v ? = ? 15 v, wr = 0 rs = 2.4 v, v in = 2.4 v, 0.8 f f temp b typ c min d max d min d max d unit analog switch analog signal range e v analog full ? 15 15 ? 15 15 v drain-source on-resistance r ds(on) v d = , i s = ? 200 a room full 270 400 500 450 550 greatest change in r ds(on) between channels f r ds(on) ? 10 v < v s < 10 v room 6 % source off leakage current i s(off) v en = 0 v, v s = 10 v v d = 10 v room full 0.005 ? 1 ? 50 1 50 ? 5 ? 50 5 50 drain off v en = 0 v dg528 room full 0.015 ? 10 ? 200 10 200 ? 20 ? 200 20 200 drain off leakage current i d(off) v d = 10 v v s = 10 v DG529 room full 0.008 ? 10 ? 100 10 100 ? 20 ? 100 20 100 na drain on v s = v d = v dg528 room full 0.03 ? 10 ? 200 10 200 ? 20 ? 200 20 200 drain on leakage current i d(on) v s = v d = v v en = 2.4 v DG529 room full 0.015 ? 10 ? 100 10 100 ? 20 ? 100 20 100 digital control logic input current v a = 2.4 v room hot ? 0.002 ? 10 ? 30 ? 10 ? 30 input voltage high i ah v a = 15 v room hot 0.006 10 30 10 30 a logic input current input voltage low i al v en = 0 v, 2.4 v, v a = 0 v rs = 0 v, wr = 0 v room hot ? 0.002 ? 10 ? 30 ? 10 ? 30 dynamic characteristics transition time t trans see figure 5 room 0.6 1 break-before-make interval t open see figure 4 room 0.2 en and wr turn-on time t on(en, wr) see figures 6 and 7 room 1 1.5 s en and wr turn-off time t off(en, wr) see figures 6 and 8 room 0.4 1 charge injection q v s = 0 v, r y = 0 c l = 10 f room 4 pc off isolation oirr v en = 0 v, r l = 1 k c l = 15 pf v s = 7 v rms, f = 500 khz room 68 db logic input capacitance c in f = 1 mhz room 2.5 source off capacitance c s(off) v en = 0 v, v s = 0 v f = 140 khz room 5 pf v en = 0 v dg528 room 25 pf drain off capacitance c d(off) v d = 0 v f = 140 khz DG529 room 12 minimum input timing requirements write pulse width t w full 300 300 a x , en setup time t s full 180 180 a x , en hold time t h full 30 30 ns reset pulse width t rs v s = 5 v, see figure 3 full 500 500
dg528/529 vishay siliconix www.vishay.com 4 document number: 70068 p-32167 ? rev. c, 15-nov-93

test conditions unless otherwise specified a suffix ? 55 to 125 c b, c, d suffix ? 40 to 85 c parameter symbol v+ = 15 v, v ? = ? 15 v, wr = 0 rs = 2.4 v, v in = 2.4 v, 0.8 f f temp b typ c min d max d min d max d unit power supplies positive supply current i+ room 2.5 2.5 negative supply current i ? v en = 0 v, v a = 0 room ? 1.5 ? 1.5 ma notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function.

? 20 ? 15 ? 10 ? 505101520 500 400 300 200 100 r ds(on) vs. v d and power supply v d ? drain voltage (v) 7.5 v r ds(on) ? drain-source on-resistance ( 10 v 15 v 20 v t a = 25 c ? 15 ? 10 ? 5051015 0 ? 20 ? 40 ? 60 leakage currents vs. analog voltage i d(off) i d(on) i s(off) 15 v supplies t a = 25 c (pa) i , i sd v analog ? analog voltage (v) 2.5 2.0 1.5 1.0 0.5 0 input switching threshold vs. v+ and v? supply voltages v+, v ? positive and negative supplies (v) t a = 25 c (v) t v 0 5 10 15 20 supply currents vs. toggle frequency i+, i ? (ma) 1 k 10 k 100 k 1 m 4 3 2 1 0 i+ i ? toggle frequency (hz) )
dg528/529 vishay siliconix document number: 70068 p-32167 ? rev. c, 15-nov-93 www.vishay.com 5

figure 1. v+ v+ v+ latches en clk reset a x wr rs v ref d o d n q o q n level shift v+ v ? v ? v ? v ? gnd v ? v+ d v ? v+ decode s 1 v ? v+ v ? v+ v+ s n

the internal structure of the dg528/DG529 includes a 5-v logic interface with input protection circuitry followed by a latch, level shifter, decoder and finally the switch constructed with parallel n- and p-channel mosfets (see figure 1). the logic interface circuit compares the ttl input signal against a ttl threshold reference voltage. the output of the comparator feeds the data input of a d type latch. the level sensitive d latch continuously places the d x input signal on the q x output when the wr input is low, resulting in transparent latch operation. as soon as wr returns high, the latches hold the data last present on the d x input, subject to the minimum input timing requirements. following the latches the q x signals are level shifted and decoded to provide proper drive levels for the cmos switches. this level shifting insures full on/off switch operation for any analog signal present between the v+ and v ? supply rails. the en pin is used to enable the address latches during the wr pulse. it can be hard-wired to the logic supply or to v+ if one of the channels will always be used (except during a reset) or it can be tied to address decoding circuitry for memory mapped operation. the rs pin is used as a master reset. all latches are cleared regardless of the state of any other latch or control line. the wr pin is used to transfer the state of the address control lines to their latches, except during a reset or when en is low (see truth tables). figure 2. figure 3. 3 v 0 3 v 0 50% 80% 80% en 3 v 0 0 50% t w t s t h t rs t off (rs) wr rs a 0 , a 1 , (a 2 ) 80% v o switch output
dg528/529 vishay siliconix www.vishay.com 6 document number: 70068 p-32167 ? rev. c, 15-nov-93

figure 4. break-before-make dg528 DG529 en v+ gnd v ? +5 v 35 pf ? 15 v +15 v +2.4 v rs a 0 , a 1 , (a 2 )d b , d all s and d a wr 300 v o 50 logic input switch output v o v s t open t r <20 ns t f <20 ns 3 v 0 v 50% 80% 0 v dg528 DG529 figure 5. transition time s 1b s 1a ? s 4a , d a s 2b and s 3b d b rs a 0 a 1 50 wr 300 v o 10 v 10 v s 4b en v+ gnd v ? 35 pf ? 15 v +15 v +2.4 v rs s 1 s 2 ? s 7 a 0 a 1 a 2 50 wr 300 v o s 8 10 v 10 v en v+ gnd v ? d 35 pf ? 15 v +15 v +2.4 v 3 v 0 v logic input switch output v s8 v o t trans t r <20 ns t f <20 ns s 8 on s 1 on t trans 0 v v s1 50% 10% 90%
dg528/529 vishay siliconix document number: 70068 p-32167 ? rev. c, 15-nov-93 www.vishay.com 7

figure 6. enable t on /t off time dg528 DG529 rs en +2.4 v s 1 s 2 ? s 8 a 0 a 1 a 2 50 wr 300 v o v+ gnd v ? d ? 5 v 35 pf ? 15 v +15 v s 1b s 1a ? s 4a , d a s 2b ? s 4b rs d b a 0 a 1 50 wr 300 v o en +2.4 v v+ gnd v ? ? 5 v 35 pf ? 15 v +15 v logic input switch output v o t r <20 ns t f <20 ns 3 v 0 v 0 v t off(en) t on(en) 50% 90% v o figure 7. write turn-on time t on(wr) 3 v 0 v 0 v 50% dg528 DG529 wr switch output v o 20% t on(wr) a 0 , a 1 , (a 2 ) d b , d en wr 300 w remaining switches s 1 or s 1b v o rs v+ gnd v ? +5 v 35 pf ? 15 v +15 v +2.4 v
dg528/529 vishay siliconix www.vishay.com 8 document number: 70068 p-32167 ? rev. c, 15-nov-93

figure 8. reset turn-off time t off(rs) 3 v 0 v 0 v 50% dg528 DG529 rs switch output v o 80% t off(rs) rs v o en remaining switches wr s 1 or s 1b d b , d a 0 , a 1 , (a 2 ) 300 w v+ gnd v ? +5 v 35 pf ? 15 v +15 v +2.4 v data bus reset address decoder address bus +5 v en v+ v ? d +15 v ? 15 v dg528 processor system bus 15 v analog inputs analog output wr rs s 1 s 8 a 0 , a 1 , a 2 , write figure 9. bus interface
dg528/529 vishay siliconix document number: 70068 p-32167 ? rev. c, 15-nov-93 www.vishay.com 9

v+ positive supply voltage (v) v ? negative supply voltage (v) v in logic input voltage v inh(min) /v inl(max) (v) v s or v d analog voltage range (v) 20 15 b 8 c ? 20 ? 15 ? 8 (min) 2.4/0.8 2.4/0.8 2.4/0.8 20 15 8 notes: a. application hints are for design aid only, not guaranteed and not subject to production testing. b. electrical parameter chart based on v+ = 15 v, v l = 5 v, v r = gnd. c. operation below 8 v is not recommended. the dg528/DG529 minimize the amount of interface hardware between a microprocessor system bus and the analog system being controlled or measured. the internal ttl compatible latches give these multiplexers write-only memory, that is, they can be programmed to stay in a particular switch state (e.g., switch 1 on) until the microprocessor determines it is necessary to turn different switches on or turn all switches off (see figure 9). the input latches become transparent when wr is held low; therefore, these multiplexers operate by direct command of the coded switch state on a 2 , a 1 , a 0 . in this mode the dg528 is identical to the popular dg508a. the same is true of the DG529 versus the popular dg509a. during system power-up, rs would be low, maintaining all eight switches in the off state. after rs returned high the dg528 maintains all switches in the off state. when the system program performs a write operation to the address assigned to the dg528, the address decoder provides a cs active low signal which is gated with the write (wr ) control signal. at this time the data on the data bus (that will determine which switch to close) is stabilizing. when the wr signal returns to the high state, (positive edge) the input latches of the dg528 save the data from the data bus. the coded information in the a 0 , a 1 , a 2 and en latches is decoded and the appropriate switch is turned on. the en latch allows all switches to be turned off under program control. this becomes useful when two or more dg528s are cascaded to build 16-line and larger multiplexers.

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